1. Field of the Invention
This invention generally relates to CMOS transistor circuitry and, more particularly, to an improved differential charge-pump suitable for use in a phase-locked loop (PLL) control system.
2. Description of the Related Art
FIG. 1 is a schematic block diagram of a conventional phase locked loop (prior art). A phase detector (or frequency detector) receives a first input signal, such as might be supplied on a serial data stream or a clock source, and compares it to a second input signal supplied by the divider. The phase detector (PD) generates an output that is responsive to difference in timing between the two input signals. The charge-pump is typically added to improve the response of the PLL, as the phase detector output does not necessarily have enough drive to instantaneously charge (or discharge) the loop filter reactances. The loop filter is typically a low-pass filter, and is used to control the overall loop response. The voltage controlled oscillator (VCO) supplies an output frequency that is responsive to the input voltage level. The loop is locked when the phase detector inputs match. The divider may be inserted in the path between the VCO and the phase detector.
Charge-pump PLL architecture offers two important advantages: 1) the capture range is only limited by the VCO output frequency range; 2) the static phase error is zero if mismatches and offsets are negligible, as the charge-pumps provide an infinite gain for a static phase difference at the input of the PFD. A wide acquisition range is often necessary because the VCO center frequency may vary considerably with process and temperature. In many applications, the acquisition range of a conventional PLL is inadequate. Since the output of charge-pump is directly connected to the loop filter, the VCO performance is highly dependent upon the quality of charge-pump. Noise generated or transferred by the charge-pump appears as VCO phase noise. Furthermore, a low output swing charge-pump translates into a smaller VCO tuning range, and smaller PLL acquisition range. To build a PLL with low jitter and a large capture range, a high performance low-noise charge-pump is required.
FIG. 2 is a schematic drawing illustrating a conventional differential charge-pump (prior art). Any noise generated by power supplies, radiated frequency sources, or conducted frequency sources, introduced into PLL signal voltages, can be translated into VCO frequency jitter. These noise susceptibilities can be reduced through the use of differential signals. Noise that becomes superimposed on a differential signal is effectively cancelled. To that end, differential charge-pumps have been designed to condition the differential outputs of a phase detector.
FIG. 3 is a timing diagram illustrating the output of the phase detector in the lock condition (prior art). Tref is the total time period of reference clock and Treset is the reset pulse width for avoiding death zone in phase detector. As shown in FIG. 2, the outputs of the charge-pump, Vout+ and Voutxe2x88x92, are always connected to loop filter, during both the Treset and Ts periods. In other words, the noise contributed from charge-pump is added to the VCO control voltage, through the loop filter, at all times. Obviously, this architecture can be a source of jitter. The other drawback of this approach is that the output voltage range is limited by both p-type and n-type current sources: Icp and Icn. In general, those current sources consist of cascaded transistors with small voltage output swings.
It would be advantageous if a differential charge-pump could be made more responsive for use in large output voltage swing PLL applications.
It would be advantageous if a differential charge-pump could be disconnected from the loop filter when a PLL was locked, to reduce VCO jitter.
The present invention is an improved differential charge-pump. The fully differential charge-pump provides a lower output noise and increased output swing, as compared to conventional designs. The performance of the improved charge-pump makes it suitable for use in CMOS OC-192 transceiver applications, for example.
Accordingly, a method is provided for conditioning the phase detector output in a PLL including a phase detector, a charge-pump, and a loop filter. The method comprises: accepting a pair of differential phase detector (PD) output signals (up/upb and dn/dnb); connecting each pair of differential PD outputs to first and second charge-pump differential sections; supplying differential charge-pump outputs (Vout+/Voutxe2x88x92) in response to the pair of differential PD output signals; and, disconnecting the charge-pump differential section outputs from the loop filter inputs when the PD differential outputs (up/dn and upb/dnb) are equal (when the loop is locked).
In some aspects, supplying differential charge-pump outputs (Vout+/Voutxe2x88x92) in response to the pair of differential PD output signals includes sourcing a first current through the first charge-pump differential section and sourcing a second current through the second charge-pump differential section. Then, the method further comprises maintaining the first current equal to the second current.
Additional details of the above-described charge-pump are provided below.